1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a method of fabricating interconnect.
2. Description of the Related Art
With the advance of semiconductor technology, the surface of a chip cannot provide sufficient area for fabricating a metal interconnect due to the device minimization and high integration density. In order to satisfy the area requirement of the metal interconnect after the device minimization, a multiple metal layer design has been developed.
In the prior art interconnect process, a dielectric layer is formed over the substrate with devices thereon. The dielectric layer can be, for example, a silicon oxide layer. An anisotropic etch process then is performed to form an opening in the dielectric layer. The bottom of the opening exposes a portion of the device or a portion of the dielectric layer, for example. A copper metal layer is formed over the substrate to fill the opening. An etch-back process, such as a chemical-mechanical polish (CMP), is performed to remove a portion of the copper metal layer so as to expose the surface of the dielectric layer.
However, there are some issues related to the interconnect process and structure. For example, the etch process described above not only planarizes the copper metal layer, but also removes a portion of the dielectric layer. That causes the damage to the surface of the dielectric layer. In addition, due to the surface damage of the dielectric layer, seams are likely formed in the subsequent dielectric barrier layer that affects process reliability.
In order to overcome the issues described above, in a prior art method of fabricating interconnect, an etch-back process is performed to the dielectric layer after the formation of the interconnect structure. The etch-back process removes the damaged surface of the dielectric layer. A low-k dielectric layer then is deposited. Another etch-back process is performed to the low-k dielectric layer. This method can diminish the surface damage of the dielectric layer and reduce the impact to the subsequent process. During the etch-back process to the dielectric layer, the surface of the copper metal layer, however, is damaged.
U.S. Pat. No. 6,413,854B1 discloses a method of fabricating a multi-layer structure. A material layer is formed on a metal layer of an interconnect structure by an electroless plating process. The surface of the metal layer, which is subject to the damage in the subsequent etch process to the dielectric layer, can be protected. U.S. Pat. No. 6,551,924B1 discloses an etch process of a dielectric layer after a metallization process. A protection layer is formed on the metal layer by a plasma etch process. In addition, a portion of the dielectric layer is etched as well. “Successful Dual Damascene Integration of Extreme Low k Materials (k<2.0) Using a Novel Gap Fill Based Integration Scheme”, published in IEEE IEDM, S. Nitta et al., 2004, discloses a method of fabricating an interconnect with the etch-back/gap-fill (EBGF) process to a dielectric layer. While a CMP process planarizes a refilled dielectric layer, a cap layer is formed on the metal layer to protect the surface of the metal layer from damage.